0512-63414949-80512
Service hotline
Chip Journey: Exploring the Endless Mysteries of Semiconductor Packaging Technology
2023-12-29
Semiconductor packaging is a series of processing steps, including wafer slicing, mounting, bonding, plastic packaging, electroplating, and rib cutting, carried out on tested wafers to obtain semiconductor products with certain functions. The packaging and testing process enables the chip to work reliably and stably. The quality of packaging technology directly affects the normal use of chips. One of the standards for measuring packaging technology is the ratio of chip area to packaging area, and the closer the ratio is to 1, the better. In the packaging and testing industry chain, the upstream mainly includes packaging and testing equipment and packaging materials, the midstream is packaging and testing manufacturers, and the downstream is Fabless manufacturers and IDM manufacturers.
Semiconductor packaging and testing industry chain:
In terms of packaging development process, chip design and packaging design development will be synchronized to optimize the overall thermal performance. Feasibility studies will be conducted by packaging related departments, including rough testing of packaging design to facilitate electrical, thermal, and structural evaluation and analysis, in order to avoid problems during mass production. Packaging manufacturing and thermal and reliability testing will be conducted afterwards.
The packaging process is relatively complex and involves multiple steps. The entire process mainly includes incoming material inspection, film application, grinding, mounting, dicing, mounting, bonding, plastic sealing, deburring, electroplating, cutting and bending, quality inspection, and product shipment. Each process step is indispensable.
Semiconductor packaging process:
Source: Minmetals Whole Volume Research Institute
The main function of semiconductor packaging is to seal chips and devices in packaging materials such as epoxy resin molded plastic (EMC), protecting them from physical and chemical damage. The core includes four main functions: mechanical connection, mechanical protection, electrical connection, and heat dissipation. The four major functions of integrated circuit packaging:
1. Chip electrical thermal retention function: Through the advancement of packaging technology, it meets the constantly evolving requirements of high performance, miniaturization, high-frequency, etc., ensuring the functionality of the chip.
2. Chip protection function: Protect the surface of the chip and the connecting leads to prevent electrical or physical damage from external forces and environmental influences
3. Stress relief function: Stress can be generated due to external environmental influences or chip heating. Packaging can alleviate stress, prevent chip damage and failure, and ensure reliability.
4. Size adjustment coordination function: Adjust the fine lead spacing of the chip to the size spacing of the actual substrate, making it easier for actual installation operations.
Semiconductor packaging function:
Source: Minmetals Whole Volume Research Institute
The development of packaging technology has always been iterative with the constant upgrading of user demand for products. From a technical perspective, heat dissipation, miniaturization, low cost, high reliability, stacking, and high-speed signal transmission are the development trends of packaging technology. In terms of heat dissipation, materials with good thermal conductivity and packaging structures that can effectively dissipate heat are used; Miniaturization can compress the packaging volume, leaving more space for other materials such as batteries and cameras; Due to the limitation of chip speed caused by packaging, packaging technology that supports highspeed electrical signal transmission has also become an important development trend, thereby improving transmission speed; 3D stacking technology can achieve stacking multiple chips within a single packaging shell.
The global integrated circuit packaging technology has gone through five stages of development. The first stage was before the 1970s, when throughhole plug transformation packaging was adopted; The second stage was after the 1980s when surface mount packaging was adopted; At present, the mainstream packaging technologies worldwide are in the third stage, mainly based on Ball Grid Array (BGA) and Chip Level Packaging (CSP), and are gradually iteratively upgrading to the fourth and fifth stage technologies represented by 3D, SiP, Flip Solder (FC), on-chip bumping, TSV, Fan Out, and Fan In.
Development stage of integrated circuit packaging:
Packaging is generally divided into four levels:
Zero level packaging: Complete wafer manufacturing, cut the wafer into bare chips, and the fabrication of bare chip electrodes and the connection of leads are all completed on the silicon wafer;
Level 1 packaging: Chip level packaging, which encapsulates the chip in a packaging substrate or lead frame to complete sealing protection and circuit wiring;
Level 2 packaging: Electronic assembly, combining packaged chips on a circuit board;
Level 3 packaging: Electronic whole system, combining several circuit boards on a motherboard or combining several subsystems into a complete electronic product.
Data source: Yole
There are various ways to classify semiconductor packaging, which can be divided into metal packaging, ceramic packaging, metal ceramic packaging, and plastic packaging according to material classification. Among them, plastic packaging accounts for more than 95% of the global integrated circuit market. According to shape classification, it can be divided into pin insertion type, surface mount type, and high-density packaging. According to the number of integrated circuit chips in packaging, it can be classified into single chip packaging and multi chip packaging. According to the distribution pattern of pins, they can be classified into single-sided pin packaging, double-sided pin packaging, quadrilateral pin packaging, and bottom pin packaging.
Packaging technology classification:
Source: New Materials Online
